Wearable ECG Holter Monitor
Wearable ESP32 + AD8232 node that streams real-time ECG over Wi-Fi through an 8-stage DSP pipeline to a live browser dashboard.
- ESP32
- Django Channels
- SciPy
- Chart.js
About
Who I am
I enjoy turning ideas into simple pages. I focus on clarity, usability, and readable code.
- HTML & CSS
- JavaScript
- Responsive design
- Accessibility
Projects
Recent work
32-bit RISC-V Processor (UART + VGA)
Custom RV32I CPU on the DE10-Lite FPGA — instructions streamed over UART through a 5-stage pipeline with valid/flush handshakes, register state on VGA.
- Verilog
- RISC-V
- FPGA
- VGA
Pipelined RV32I RISC-V Core
Five-stage RV32I core in SystemVerilog with a forwarding/stall/flush hazard unit — verified across the full rv32-bmarks suite (64/64 pass).
- SystemVerilog
- RV32I
- Pipeline
- Verification
32-bit ALU — RTL to GDSII
Complete Cadence ASIC flow for a bit-slice 32-bit ALU on GPDK045 45 nm — RTL, synthesis, place-and-route, signoff and pad-frame integration.
- Verilog
- Cadence
- 45 nm
- ASIC
YUPlanner
Three-tier academic planner — React SPA + Spring Boot REST API + MySQL — with course scheduling, professor ratings and PDF export across student/professor/advisor roles.
- React
- Spring Boot
- MySQL
- REST
Project Six
A short description of what this project is and what problem it solves.
- Tool A
- Tool B
Contact
Let’s talk
Email: salwan.aldhahab@gmail.com
LinkedIn: linkedin.com/in/salwan-aldhahab
GitHub: github.com/salwan-aldhahab